(1). Field of the Invention
The present invention relates to a level shifter circuit for use in a semiconductor integrated circuit device in which circuits are operated by different voltages, in particular relates to a level shifter circuit which shifts the level of the signal output from a low-voltage operating circuit and outputs a level-shifted signal to a high-voltage operating circuit.
(2). Description of the Prior Art
FIG. 1 is a circuit diagrams showing a configurational example of a conventional level shifter circuit (c.f. Japanese Patent Application Laid-Open Hei 7 No. 193488).
This level shifter circuit includes low-voltage operating inverters INV1 and INV2, a high-voltage operating inverter INV3, N-channel MOS (to be abbreviated as NMOS hereinbelow) transistors NT1, NT2, NT3 and NT4 and P-channel MOS (to be abbreviated as PMOS hereinbelow) transistors PT1 and PT2. The output from low-voltage operating inverter INV1, the input to low-voltage operating inverter INV2, the gates of NMOS transistors NT1 and NT3 are joined. The output from low-voltage operating inverter INV2 is connected to the gates of NMOS transistors and NT2 and NT4. The input to high-voltage operating inverter INV3, the drains of NMOS transistors NT2 and PMOS transistors PT2, the gate of PMOS transistor PT1 and the source of NMOS transistor PT3 are joined. The drains of NMOS transistor NT1 and PMOS transistor PT1 and the gate of PMOS transistor PT2 and the source of NMOS transistor NT4 are joined. The sources of PMOS transistors PT1 and PT2 and the drains of NMOS transistors NT3 and NT4 are connected to the power feed line from a high-voltage power source. The input to low-voltage operating inverter INV1 forms an input signal terminal Vin1 while the output from high-voltage operating inverter INV3 forms an output signal terminal Vout1.
Next, the operation of the thus configured level shifter circuit will be described. When a signal which transits from a VSS level (to be referred to as `the L-level` hereinbelow) to a VDD1 level (to be referred to as `the H-level` hereinbelow) is supplied from a low-voltage operating circuit to input signal terminal Vin1, the output signal from low-voltage operating inverter INV1 transits from the H-level to the L-level. With this transition, the ON-state resistance of NMOS transistor NT1 and that of NT3 gradually increase, so the source-drain voltage of NMOS transistor NT1 and that of NT3 increase. At almost the same time, the output signal from low-voltage operating inverter INV2 transits from the L-level to the H-level so that NMOS transistors NT2 and NT4 become activated with their resistances gradually becoming lowered and hence the voltages of NMOS transistors NT2 and NT4 between source and drain become lowered. The activation of NMOS transistor NT4 raises the potential at the gate of PMOS transistor PT2 to a midway voltage so that the ON-state resistance rises. This causes NMOS transistor NT2 to lower the potential at a node n2. Simultaneously, the lowered potential at node n2 lowers the ON-state resistance of PMOS transistor PT1 while raising the potential at a node nl. When input signal terminal Vin1 from the low-voltage operating circuit definitely reaches the H-level, NMOS transistors NT1 and NT3 are turned off, NMOS transistors NT2 and NT4 are turned on, PMOS transistor PT1 is turned on, and PMOS transistor PT2 is turned off. Thereby the output signal terminal Vout1 to the high-voltage operating circuit becomes stabilized and set at a VDD2 level (to be referred as `the HH level`).
On the other hand, when a signal which transits from the L-level to the H-level is supplied from the low-voltage operating circuit to input signal terminal Vin1, the output signal from low-voltage operating inverter INV1 transits from the L-level to the H-level. With this transition, the ON-state resistance of NMOS transistor NT1 and that of NT3 gradually become lowered, so the source-drain voltage of NMOS transistor N1 and that of NT3 become lowered. At almost the same time, the output signal from low-voltage operating inverter INV2 transits from the H-level to the L-level so that NMOS transistors NT2 and NT4 become inactive with their resistances gradually increasing and hence the voltages of NMOS transistors NT2 and NT4 between source and drain increase. The activation of NMOS transistor NT3 raises the potential at the gate of PMOS transistor PT1 to a midway voltage so that the ON-state resistance rises. This causes NMOS transistor NT1 to lower the potential at a node n1. Simultaneously, the lowered potential at node n1 lowers the ON-state resistance of PMOS transistor PT2 while raising the potential at a node n2. When input signal terminal Vin1 from the low-voltage operating circuit definitely reaches the L-level, NMOS transistors NT1 and NT3 are turned on, NMOS transistors NT2 and NT4 are turned off, PMOS transistor PT1 is turned off, and PMOS transistor PT2 is turned on. Thereby the output signal terminal Vout1 to the high-voltage operating circuit becomes stabilized and set at the L-level.
The above conventional level shifter circuit, however, suffers from the following drawback. That is, in the conventional level shifter circuit, for example, when a signal changing from the L-level to the H-level is supplied from the low-voltage operating circuit to input signal terminal Vin1, the output signal from low-voltage operating inverter INV1 changes from the H-level to the L-level while the output signal from low-voltage operating inverter INV2 changes from the L-level to the H-level. Upon these transitions, the change of the output signal from low-voltage operating inverter INV2 lags behind the change of the output signal from low-voltage operating inverter INV1. Therefore, NMOS transistors NT1, NT2, NT3 and NT4 and PMOS transistors PT1 and PT2 are temporarily turned off, causing potential instability at nodes n1 and n2 and hence producing difficulties in operating the level shifter at high speeds. The same drawback occurs when a signal changing from the H-level to the L-level is supplied from the low-voltage operating circuit to input signal terminal Vin1.